A portable two-channel acquisition instrument, designed around 100 MHz analog bandwidth and USB-C. The current candidate retains all 14 ADC bits at 400 MS/s per channel, with a documented simulation trail and explicit limits on what those simulations establish.
Fig. 1 — Candidate architectureThe proposed instrument: two simultaneous analog channels and a shared acquisition path. This is an architecture diagram, not a fabricated board or a completed hardware schematic.
The project began when the LTspice automation tool was mature: choosing a real acquisition architecture, turning its analog path into executable netlists, and checking the decisions against saved waveforms. Each channel uses a compensated range divider, a high-impedance buffer, differential amplification, programmable gain and a passive anti-alias filter ahead of a dual ADC.
The development baseline is 400 MS/s per channel. Two channels at 14 bits generate 1.4 GB/s before framing. That points toward an FPGA and FX20 bridge on a qualified USB 20 Gbps host, with memory for triggered acquisition and host stalls. USB-C describes the connector; it does not guarantee that a particular computer can sustain this stream.
This is a design in progress. The evidence covers a representative analog channel with vendor macro-models and an approximate ADC input load. It does not yet establish two-channel crosstalk, converter SINAD, USB throughput or finished-board performance.
OPA817 → LMH5401 → LMH6401 → nine-pole differential filter, evaluated across input ranges and gain settings.
Generated netlists, simulator logs, RAW waveforms, script snapshots and hashes identify exactly what produced each result.
Eight selected corners and 64 seeded L/C variations test response margin within declared assumptions.
A lossless 14-bit packing reference and explicit host, buffer and memory-bandwidth calculations.
Start with three separate requirements: preserve the 0–100 MHz signal band within ±0.5 dB, put the −3 dB cutoff above 100 MHz, and reject signals that would alias into the retained band. A part labeled 100 MHz cannot satisfy all three by itself. The connected circuit, its loads, sampling clock and physical layout must be designed together.
The current synthesis uses a 125 MHz low-pass filter and 400 MS/s per channel. The saved analog model reaches about 123.81 MHz at −3 dB; this is connector-referenced and excludes the external probe. The walkthrough below separates retained simulation evidence, an interactive ideal-filter calculation, and parameters that still need PCB extraction or bench qualification.
A / Design the complete transfer function
01 / Preserve the input
A high DC resistance is not a high RF impedance. Probe, relay, clamp and pad capacitances load the source and change divider compensation.
Rt × Ct ≈ Rb × Cb,total
100:1 model: 990 kΩ × 2 pF = 10 kΩ × 198 pF. The bottom total includes buffer/protection capacitance; the external probe is not modeled.
02 / Isolate the divider
The FET-input buffer separates the high-impedance divider from the low-impedance differential stage. Closed-loop flatness, input capacitance and large-signal response matter together.
Unity gain · ±6 V rails
TI lists 800 MHz small-signal and 250 MHz large-signal bandwidth at 2 Vpp. Neither is the bandwidth of this complete channel.
03 / Allocate gain and swing
Convert to differential, then set gain without clipping an intermediate stage. Feedback resistors, noise gain, source/load impedance and common-mode control change the usable response.
~2.80 V/V at nominal code 21
1:1 connector-to-ADC DC gain. A 0.3 V peak input gives ~0.84 V differential peak before overshoot. Higher gain needs a smaller input.
04 / Shape the bandwidth
A 125 MHz synthesis cutoff leaves the 100 MHz band relatively flat. More poles steepen rejection but increase component sensitivity, ringing and layout complexity.
~123.81 MHz modeled −3 dB
Seven poles miss the saved rejection check. Nine pass, with ~14.5–16.4% step overshoot. Bessel-like shaping favors pulse fidelity; elliptic zeros trade ripple and sensitivity for selectivity.
05 / Sample the signal
The converter needs enough analog input bandwidth and sampling speed. Its buffered input still requires a real drive/settling model and a quiet reference and clock.
2 Vpp differential · 1.4 V CM
The LTspice endpoint is only a 100 Ω || 2 pF load. It does not simulate conversion, clock jitter, sampling kickback or silicon distortion.
06 / Move and power the data
Sampling faster relaxes filtering, but grows traffic, FPGA activity and thermal demands. Memory absorbs finite stalls; it cannot fix a persistent throughput deficit.
1.4 GB/s payload at 400 MS/s
512 MiB holds ~335.5 ms in 16-bit containers. Input power is ~9.1 W estimated / 14.0 W allocated; USB-C power and USB 20 Gbps service need qualification.
Loaded stage responses multiply; their gains in dB add. As a teaching example, three isolated, identical 100 MHz single-pole stages produce only ~51 MHz combined −3 dB bandwidth. Real feedback stages are more complex: simulate the connected circuit with its terminations.
Htotal(f) = Hdivider × Hbuffer × Hgain × Hfilter
A sine needs a peak slope of 2πfVpk. At 100 MHz and 0.3 V peak that is ~188 V/µs at the buffer. Check slew, output current, headroom and distortion at each stage, then verify step overshoot and settling. A flat AC sweep alone cannot establish a full-scale input rating.
Input example: 10 pF has |Xc| ≈ 159 Ω at 100 MHz, even when the port is labeled 1 MΩ at DC. The external 10×/100× probe, cable and compensation therefore need their own end-to-end bandwidth check.
B / Sampling buys filter transition room
Keep a 0–100 MHz signal band. The first higher-frequency band that folds into it starts at sample rate minus 100 MHz. Raising the sample rate moves that boundary away; raising the filter cutoff improves flatness but weakens rejection.
Swipe the chart to see the full frequency axis →
Droop at 100 MHz
0.078 dB
Within illustrative 0.5 dB limit
Rejection at 300 MHz
68.4 dB
Ideal edge clears 60 dB
Two-channel payload
1.400 GB/s
14 bits retained; before framing
Required host service
1.653 GB/s
Framing + 15% spare service time
400 MS/s is the compromise: the alias band starts at 300 MHz and the host target is about 1.653 GB/s. Actual host/controller/cable performance still needs qualification.
The retained band is a processing choice, not the whole Nyquist band. A digital low-pass filter is still required before decimation; it cannot remove signals already aliased into 0–100 MHz. Neither decimation nor sample rate alone increases analog bandwidth.
Source: Infineon FX20 throughput FAQC / Make physical assumptions visible
These are the present netlist placeholders and unmodeled effects. They are not fabrication tolerances or released PCB constraints.
1 fF / leg bypass
66.76 dB
Minimum 300 MHz–1 GHz rejection
Saved passive study · passes
5 fF / leg bypass
52.79 dB
Minimum 300 MHz–1 GHz rejection
Saved passive study · fails
50 fF / leg bypass
32.81 dB
Minimum 300 MHz–1 GHz rejection
Saved passive study · fails
CPORT = 2 pF (50 Ω), 10 pF (1:1), 8 pF (attenuated); CPROT = 0.3 pF at buffer.
Replace with probe/connector/relay/clamp C(V), pad capacitance and compensation trim. The 0.3 pF element is not a protection circuit.
Inductor Q = 60 at 125 MHz; parallel self-C = 0.1 pF each. Capacitor ESR = 0.05 Ω, ESL = 0.2 nH.
Use actual part values, frequency-dependent loss and vendor models; add pad/via/trace parasitics. Q at one frequency is not broadband qualification.
Cfeed = 1 fF per leg nominal. Saved sweep: 0, 1, 5, 10 and 50 fF.
Extract capacitive and magnetic coupling. Keep input/output physically separated and return paths controlled. 1 fF is an assumption, not a proven layout budget.
Rdiff = 100 Ω; Cdiff = 2 pF.
Check actual ADC impedance versus frequency, driver settling, reference loading and sampling effects. Validate at the selected clock rate and amplitude.
ΔCpad, Lvia, trace delay, impedance error and mutual coupling: TBD.
Choose stackup and extract routes before assigning numeric limits. Include leg mismatch, return inductance, two-channel crosstalk and timing skew.
90 fs external clock + 30 fs board + 75 fs aperture → 120.9 fs RSS. Ideal simulation rails.
Integrate clock phase noise for the actual mode; include supply ripple/spurs, coupling, reference noise and thermal drift. Avoid counting aperture jitter twice.
Closure sequence: select real parts → include their parasitics and loading → sweep corners and imbalance → extract the PCB → repeat AC/noise/transient checks → measure the board. Preserve a continuous reference plane with controlled current returns; set stackup and routing constraints from the actual interfaces.
D / Converter decision · reviewed 7 September 2026
Its dual 500 MS/s capability permits the 400 MS/s compromise, with buffered analog inputs, 1.4 GHz input bandwidth, LVDS output and about 0.6 W total typical converter power at 500 MS/s. The 1.4 GHz input specification is not the instrument bandwidth—and it makes an external anti-alias filter essential.
Swipe the table to compare both converters →
| Tradeoff | ADC3649 · baseline | ADC3669 · alternative |
|---|---|---|
| Raw output resolution | 14 bits | 16 bits |
| Typical SNR | 73.8 dBFS | 75.6 dBFS |
| Typical SINAD | 71.9 dBFS | 73.7 dBFS |
| Payload at 400 MS/s × 2 | 1.400 GB/s | 1.600 GB/s |
| Host target with framing + margin | 1.653 GB/s | 1.890 GB/s |
The 16-bit alternative improves these converter-only typical figures by ~1.8 dB, not the ~12 dB implied by two ideal extra bits. Its 14.3% traffic increase narrows host margin. A 250 MS/s alternative such as AD9643 lowers traffic but brings the first alias boundary down to 150 MHz, requiring a different filter strategy. Neither is a drop-in system improvement.
The saved front-end model contributes ~207–210 µV RMS at the ADC differential input over 10 Hz–100 MHz at nominal gain. Converter noise, folded noise, clock error, supply noise and distortion remain additional terms. Gain can overcome downstream noise but also clips sooner; bandwidth limiting can reduce noise but cannot retain signals it filters away.
SNRjitter = −20 log₁₀(2πfinσt). At 100 MHz, 100 fs RMS gives an ~84 dB jitter-only ceiling; 200 fs gives ~78 dB. These are ceilings, not total SNR. Add independent noise powers, and do not add aperture jitter again to measured ADC noise that already includes it.
All 12 nominal range/gain cases meet the proposed bandwidth, flatness and rejection checks. The complete modeled chain reaches about 123.81 MHz at −3 dB. Its worst relative gain at 100 MHz is −0.2672 dB, and minimum attenuation across the checked 300 MHz–1 GHz stopband is 69.28 dB.
At 400 MS/s, 300 MHz is the first frequency above Nyquist that folds into the retained 0–100 MHz band. The filter target is at least 60 dB attenuation over 300 MHz–1 GHz. These are engineering study thresholds, not a released instrument specification.
All eight selected corners pass, with bandwidth from 118.89 to 128.66 MHz and a passband envelope of −0.4549 to +0.1728 dB. The separate seeded study varies each inductor uniformly by ±5% and each capacitor by ±2%: all 64 cases pass, with minimum rejection of 68.04 dB.
The corner combinations are selected, not exhaustive. The 64-run study varies L/C only, with other assumptions held nominal. Neither result is a production-yield guarantee, and synthesized component values still need replacement with actual part models.
A filter can look excellent until the model includes a path around it. Adding 1 fF of input-to-output coupling per differential leg leaves 66.76 dB minimum rejection in the passive study. At 5 fF, that falls to 52.79 dB. At 50 fF, it is only 32.81 dB.
This simplified path is a sensitivity experiment, not an extracted PCB. It makes a concrete layout requirement: the stopband cannot be signed off until component parasitics, return paths and coupling are modeled and measured. The nominal circuit assumes 1 fF; that has not been demonstrated on a board.
Four input-mode pulse tests and four 100 MHz sine tests remain inside the modeled ADC voltage limits. Step rise times are about 3.89–4.05 ns, with 14.5–16.4% overshoot. The selected transient study uses a documented numerical convergence setting; invalid earlier outputs are excluded.
Retaining every ADC bit does not deliver 14 effective bits at 100 MHz. At the nominal gain setting, modeled front-end noise is approximately 207–210 µV RMS over 10 Hz–100 MHz. Maximum gain raises it substantially. Converter noise, jitter, alias-folded noise and distortion still have to be included, and the macro-model harmonics are not accurate enough to claim system SFDR or SINAD.
The Python packing reference checked 131,072 sample codes, including every signed 14-bit value in each packing position, against an independent decoder. That verifies the proposed byte format. The FPGA capture path, memory controller, FX20 firmware and host software are still implementation work.
The upper voltage target is 300 V at an appropriately rated 10×/100× probe tip on isolated low-energy circuitry. That corresponds to 30 V or 3 V at the connector, respectively, with frequency derating still to be defined. It is not a 300 V direct-input or 50 Ω termination rating.
The candidate analog channel now exists as an editable LTspice schematic. All 52 elements match the native exported netlist after parameter substitution and instance-name normalization. Its finite AC response agrees with the selected reference to within 0.000001 dB across the saved sweep.
The images below are direct screen captures from LTspice: the editable schematic in its native editor and the saved simulation data in its waveform viewer. Application titles and controls are retained. Named nets connect separated schematic sections, while the differential filter is explicitly wired.
The schematic conversion is verified. The next circuit work is real protection/relay parts, filter components and power circuitry. FPGA bank assignment, timing closure and measured USB, thermal, noise and distortion performance remain design-freeze gates.
The selected evidence set contains 114 finite runs with matching artifact hashes: 110 meet their recorded checks and four negative controls fail rejection. Noise cases only check that modeled noise is finite and positive. This count is not a claim that 114 hardware performance tests passed.
The LTspice automation engine used for this study is public. The DAQ design package and hardware are still under development; this link opens the simulation toolkit, not a released DAQ repository.