Cadence Design Automation

The two bridges look symmetric from the MCP server's side, but they exist for different reasons underneath. Capture ships a TCP server, so the client just connects to it. SKILL has no socket support at all — its only inter-process primitive is ipcBeginProcess, which spawns a child wired to stdin and stdout. So on the Allegro side, the spawned child owns the actual socket, and SKILL talks to its own child process over pipes instead.

A loopback-only starter script is included and used by default. Even bound to 127.0.0.1 it's still unauthenticated local RPC — any process on the machine can use it — a reasonable trust boundary for a design-automation channel on one workstation, but a deliberate choice to make, not a default to leave running on a shared or untrusted network.

The tooling was developed against a real design instead of a synthetic one — a moving-coil phono preamplifier, 57 parts across two schematic pages, laid out on a four-layer, 8 by 3 inch board with split ground and power planes. The board's component-level details — BOM, exact routing, net names — are intentionally not published in the automation repository; they belong with the board, which is also why per-board configuration lives in a gitignored board.json rather than in the repo itself.

The schematic it was built from, both pages. These are the source the bridge reads: the reference designators, values and node names visible here are the same ones the automation returns, and the same ones that end up in the simulation deck later on.

The renders below come from the same Allegro database — the 3D models on each footprint, the silkscreen, the solder mask, exactly as the fab package describes them. They are the closest look at the board available until real ones come back from the fab house.

The fix wasn't a better catch block. It was refusing to let a caught exception produce a value that could be mistaken for real data — the same instinct behind board.json refusing to run an unconfigured check rather than reporting a silent pass.

Reading a design is only half of it. The bridge was used to pull the schematic's pin-level connectivity out of OrCAD Capture — 32 nets, 149 pin references — and that netlist was translated into a SPICE deck, simulated in LTspice, and parsed back with the raw-file parser from the companion LTspice project. Nothing in the chain was transcribed by hand: the deck generator refuses to emit a netlist if any node ends up with fewer than two connections, so a transcription slip becomes an assertion failure rather than a plausible wrong answer.

The circuit is a moving-coil phono preamplifier: 100 ohm input loading, an LT1028 first stage with an active RIAA feedback network, and an LM4562 output stage. Measured gain at 1 kHz is 63.7 dB.

The same setup answers a question the project had previously settled by reading a datasheet legend. The RIAA capacitors were once specified at 1 percent — a target that was never sourced and got written into the documentation as though it had been achieved — then corrected to a 10 percent part, then changed to a 5 percent one. What that choice actually costs was never measured until now.

Frequency response is only half the picture. The same netlist run in the time domain shows a quarter-millivolt cartridge signal arriving at the output as 418 millivolts with the waveform intact, and sweeping the input amplitude until the output stops tracking gives the overload margin — 31 dB above normal groove level before the first decibel of compression, with the output clipping on the supply rails at just under 15 volts, exactly where a plus or minus 15 volt supply says it should.

Those plots are drawn from LTspice's output, not by LTspice — the numbers are the simulator's, the rendering is a script's, which is what makes them legible. Here is the same result as the tool itself shows it. The deck behind it carries the schematic's own node names — L_STG1_FB, L_RIAA_MID, L_STG2_CPL — rather than invented ones, which is the actual join between these two projects: the simulator is reading the design, not a copy of it.

And the deck itself, which is the artefact the bridge actually produced. Every line of it was written from what the schematic returned — component values, node names, pin order — with the analysis directives appended. It is short enough to read, which is the point: this is the whole translation layer between a schematic database and a circuit simulator.

What this does not cover is worth stating. The output stage uses a behavioural op-amp model because no vendor SPICE model ships with LTspice for that part, and the regulators are modelled as ideal rails rather than as the real low-noise parts on the board — so the supply rejection and the regulators' own noise contribution are both assumed away. The noise figures here come from the first stage's vendor model and the resistors around it, which is the dominant term for a moving-coil front end but not the whole of it. Distortion was not simulated at all. Those are the next things to measure, not things this already proves.